Field of the Invention
The invention relates to a method for producing electrically conducting connections through one or more insulating layers such as, for example, can be used to connect storage capacitors to the selection transistors in highly integrated FRAMs and DRAMs.
In highly-integrated assemblies, electrically conducting connections and/or contacts generally serve to permit a flow of electric current between electrically conducting sections which are located in different pattern levels. In accordance with the material of the upper and lower conducting pattern levels, there are, for example, silicon/silicon contacts, metal/silicon contacts or metal/metal contacts.
A damascene process is frequently applied to produce such contacts. For this purpose, a contact hole is etched with the aid of a photolithographic step through one (or more) insulating layer(s) down to a connection situated therebelow. This is followed by coating with a conducting material, mostly doped polysilicon, which fills up the etched contact hole completely. Subsequently, the conducting layer is removed as far as down to the insulating layer with the aid of a CMP step (Chemical-Mechanical Polishing) such that only a conducting filling (plug) remains in the etched hole. The plug in this way makes a conducting connection from the top side of the insulating layer to the underside of the insulating layer.
For some contacts such as, for example, for contacts made from polysilicon, which connect a noble metal electrode of a storage capacitor to the diffusion zone of a selection transistor, however, there is still a need for one or more additional conducting layers which are intended to prevent, for example, the diffusion of oxygen atoms or metal atoms into or through the contact. Typical barrier layers are, for example, iridium or iridium oxide. As a rule, the polysilicon is removed by an etching step from an upper part of the contact hole in order to produce the barrier. Subsequently, barrier material is deposited and patterned by means of a CMP step such that the barrier material remains only in the upper part of the contact hole. The barrier material is preferably deposited in this case by a sputtering method.
Unfortunately, the problem arises with this mode of procedure that filling up the contact hole with the barrier material becomes ever more difficult because of the ever smaller diameter of the contact holes. The result of this is either that it is necessary to have recourse to other, more expensive deposition methods, for example CVD methods, or that it is necessary to use an additional phototechnique to produce a depression with a larger diameter overlapping the contact hole. Both alternatives are attended by increased production costs, however.
In the case of some assemblies, for example FeRAMs, two barrier layers are generally used between the polysilicon and the lower electrode layer of the storage capacitor. The first barrier layer covers the polysilicon of the contact and generally prevents the diffusion of silicon atoms through the barrier. The second barrier layer covers the first barrier layer and generally prevents the diffusion of oxygen through the barrier. In some circumstances, a liner layer is still necessary between the polysilicon and first barrier layer, which makes an effectively conducting bonding connection between the polysilicon and first barrier layer. It frequently happens, furthermore, that the insulating layer consists of at least two silicon oxide layers, which have a different etching behavior.
If, in this regard, an electrically conducting connection is made from the lower electrode of a storage capacitor to a selection transistor, a range of further problems arise.
Void formation: because of the different etching rates of the two insulating layers, during etching of the contact hole, and/or during wet cleaning steps before filling up with the conducting filling material, a step is produced in the contact hole along the contact area of the two insulating layers. In the case of small contact hole diameters, during the subsequent coating process with the conducting filling material this step easily leads to incomplete filling which can lead to void formation, as is shown in FIG. 1. In FIG. 1, the lower insulating layer 1 on the semiconductor substrate 5 consists of a BPSG silicon oxide, while the upper insulating layer 2 consists of a silicon oxide produced using the TEOS process. An etching step or a wet cleaning step before the filling of the contact hole 6 produces a step in the contact hole 6 at the boundary layer between the two oxide layers. The conducting filling layer 3 consists of polysilicon. The void 4 is produced during coating with the polysilicon by virtue of the fact that the opening of the upper oxide layer is sealed before complete filling because of the smaller diameter.
Overetching trenches: in order to apply the second barrier layer to the first barrier layer in the contact hole region with the aid of the damascene method, it is necessary to structure on the substrate a mask which must have a corresponding opening at the feed-through. Because of a lack of control options, for example, instances of overetching can easily occur as the mask is being etched in this process, such that etching proceeds laterally past the first barrier layer, resulting in the formation of a trench next to the first barrier layer. This overetching trench can, for example, cause the second barrier layer, which is still to be applied, at the edge to come into contact in the opening with the liner or with the polysilicon such that oxidation of the polysilicon or other undesired chemical reactions occur which can lead to contact problems. FIG. 2a and FIG. 2b show two conditions under which overetching trenches can be produced in an insulating layer 10: in FIG. 2a, the mask opening is larger than the surface of the first barrier layer 11 and adhesion-promoting layer 12, such that an overetching trench 15 is formed around the first barrier layer 11 and the adhesion-promoting layer 12. A following second barrier layer would fill the overetching trench 15 and come into contact with the liner. In FIG. 2b, an overetching trench 15 is produced laterally by a misalignment of the mask opening with reference to the surface of the first barrier layer 11 and the adhesion-promoting layer 12. A second barrier layer would fill the overetching trench and, in this example, come into contact with the liner 12 and the polysilicon filling 13.
Dielectric close-off: for a good and effectively conducting adhesive contact on the polysilicon layer, the first barrier layer usually requires an adhesion-promoting layer, preferably a liner, as interlayer. However, the liner can react chemically upon contact with the second barrier layer, and this can lead to a dielectric close-off. The liner should therefore also not be in contact with the lower electrode or the capacitor dielectric. During the production of the barrier layers, it must therefore be ensured that the liner and second barrier layer do not come into contact. FIG. 3 and FIG. 4 show two variants of a conducting connection through an insulating layer 10 on a semiconductor substrate 5 according to the prior art, in the case of which the undesired contacts between the adhesion-promoting layer 12 and second barrier layer 17 occur. In FIG. 3, a platinum layer 18 is applied to the second barrier layer 17, which rests, in turn, on a first barrier layer 11, an adhesion-promoting layer 12 and a polysilicon layer 13. The critical transition points between second barrier layer 17 and adhesion-promoting layer 12 are situated at the edge of the adhesion-promoting layer. The problem in FIG. 4 scarcely differs.
It is accordingly an object of the invention to provide a method of producing an electrically conductive connection, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which lessens or avoids the above-described difficulties entirely, and in so doing permits the number of process steps to be kept as low as possible or even to be reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing an electrically conducting connection through insulating layers. The novel method comprises the following method steps:
providing a semiconductor substrate with at least one insulating layer;
applying a mask to a surface of the insulating layer;
carrying out a substantially isotropic etching step;
carrying out a substantially anisotropic etching step until an underside of the insulating layers is reached and a contact hole is produced;
removing the mask;
filling the contact hole with a first conducting material;
etching back the first conducting material down to a prescribed depth; and
filling a free region of the contact hole with at least one second conducting material.
The invention is particularly suitable for producing an electrically conducting connection between a diffusion zone and an electrode.
The method according to the invention has the advantage that it is possible with the aid of only one mask step to obtain a shape of contact hole resembling a wineglass and substantially approximates the requirement for a contact hole with a small contact hole area in the anisotropically etched region and a larger contact hole area in the isotropically etched region. Owing to the larger upper opening, this shape of contact hole facilitates complete filling both with the first and with the second conducting material. In particular, owing to the larger diameter sputtering methods can be used in the upper region to deposit the second conducting material.
Furthermore, this shape of contact hole permits a conducting connection of a very small contact on the underside of the insulating layers, for example a diffusion zone of a selection transistor, to a pattern on the upper side of the insulating layers, which can occupy somewhat more lateral space such as, for example, a lower electrode of a storage capacitor.
The larger opening of the contact hole in the upper region further makes it possible, for the purpose of etching a mask to be patterned on the contact hole, for example in order to apply a further conducting material to the second conducting material, for the second conducting material to serve as etching stop so as to preclude the overetching trenches described and their associated problems.
With standard methods, at least two mask steps are required to obtain a contact hole with a small contact hole area in the anisotropically etched region and a large contact hole area in the isotropically etched region. By contrast, one mask step produces the shape of contact hole resembling a wineglass, which functionally has the same advantages as the shape of contact hole produced in the two-mask process. One mask step saved economizes on several further process steps, and this leads to a higher yield in the production of non-defective chips, and thereby helps to lower the costs.
In accordance with an added feature of the invention, the ratio of the contact hole area in the isotropically etched region to the contact hole area in the anisotropically etched region is between 1.5 and 4, preferably between 2 and 3. Furthermore, it is preferred when the first conducting material is etched back at most as far as the anisotropically etched region of the contact hole. This avoids the need for the second conducting material to be deposited in the narrower anisotropically etched region of the contact hole.
An adhesion-promoting layer, in particular titanium, titanium nitride, titanium silicide, tantalum nitride or tantalum silicon nitride, is preferably produced between the first conducting material and the second conducting material. It is particularly preferred in this case when the patterning of the adhesion-promoting layer and of the second conducting material is performed by a common single-stage or multistage CMP step.
In accordance with an additional feature of the invention, a third conducting material is applied to the second conducting material. In accordance with an embodiment of the present invention, in this case the second conducting material is used as landing pad for the third conducting material. In this way, the adhesion-promoting layer is protected by the second conducting material against direct contact with the third conducting material. It is particularly preferred in this regard when the third conducting material is patterned with the aid of a CMP method.
In accordance with a further embodiment of the present invention, the contact hole is not yet filled up completely by the second conducting material, with the result that the third conducting material can be deposited into the as yet free region of the contact hole. It is once again possible in this way to save a mask level, which would otherwise be necessary to pattern the third conducting material. Furthermore, in this configuration there is also no direct contact between the adhesion-promoting layer and the third conducting material.
It is particularly preferred here when the patterning of the second and of the third conducting material (and, if appropriate, of the adhesion-promoting layer) is performed by a common single-stage or multistage CMP step. It can be advantageous in this case when the CMP process for the third conducting material is selective in relation to the second conducting material. In this way, the two materials can be removed separately from one another in a controlled fashion by the polishing liquid.
In accordance with a further feature of the invention, doped polysilicon is used as first conducting material. It is preferred, furthermore, when a barrier material is used as second and/or third conducting material. It is particularly preferred here when a barrier material for suppressing the diffusion of silicon atoms, in particular iridium, is used as second conducting material. It is preferred, furthermore, when a barrier material for suppressing the diffusion of oxygen atoms, in particular iridium oxide, is used as third conducting material. It is possible in this way, for example, to produce the conducting connections between the selection transistors and the storage capacitors in the ferroelectric memory cells. Consequently, the lower electrode layer of a ferroelectric capacitor can be applied to the third conducting material.
In accordance with a preferred embodiment of the present invention, an etching stop layer, in particular a silicon nitride layer, is applied before the production of an electrode, the etching stop layer being opened before the application of the electrode layer at the later support point of the electrode. The lower electrode of the storage capacitor can be patterned, for example, by a damascene method. During the following removal of material, the etching stop layer protects an oxide layer used during the damascene method against overetching trenches. This oxide layer is preferably removed again subsequently in order also to have available the side walls of the lower electrode as a capacitance-providing surface for storing charge.
It can occur owing to the process that the insulating layer consists of a lower insulating layer, an upper insulating layer and, possibly, further insulating layers therebetween. It is advantageous in this case when the isotropic etching reaches down into the lower insulating layer. Since, in this way, possible contact hole steps are situated in the wide, isotropically etched contact hole region, the formation of voids can be reliably prevented during deposition of the first conducting material.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in method for producing an electrically conducting connection, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.